A typical example of the semiconductor memory device is illustrated in FIG. 1 and largely comprises a memory cell array 1 regularly used for memorization of pieces of data information, an addressing unit 2 supplied with a multi-bit address signal AD from the outside thereof for specifying one of the memory cells, a control signal producing circuit 3 supplied with various external control signals such as, for example, a chip select signal S1 of an active low voltage level for producing internal control signals, a redundant memory cell row 4 provided with a plurality of redundant memory cells replacable with any memory cell row incorporated in the memory cell array, and a controller 5 provided in association with the redundant memory cell row 4.
The addressing unit 2 has an address buffer circuit 6 to which the multi-bit address signal AD is supplied, and the address buffer circuit 6 is operative to distribute the multi-bits of the address signal AD to a row address decoder circuit 7 and a column address decoder circuit 8. The controller 5 is provided with a redundant memory activation circuit 9, a plurality of programming circuits 10 to 11 and an AND gate 12. The redundant memory activation circuit 9 and the programming circuits 10 to 11 are supplied with a delayed chip select signal S1' produced by the control signal producing circuit 3 for activations thereof, and the address bits ax.sub.i and ax.sub.i distributed to the row address decoder circuit 7 are supplied in parallel to the programming circuits 10 to 11, respectively, to decide whether or not one of the memory cell rows replaced with the redundant memory cell row is selected for access. The AND gate 12 provides the redundant memory cell row 4 a activation signal for the activation thereof, and the activation signal is further supplied to the row address decoder circuit for restriction of the memory cell row replaced with the redundant memory cell row 4.
Turning to FIG. 2 of the drawings, there is shown the detailed circuit arrangement of each programming circuit which comprises a series of a fuse element 21, a p-channel type field effect transistor 22 and an n-channel type field effect transistor 23 coupled between a source of positive voltage level Vcc and a ground terminal, a flip-flop circuit 24 and an activation circuit 25. The delayed chip select signal S1' is supplied to the gate electrode of the p-channel type field effect transistor 22 for switching operation, but the n-channel type field effect transistor 23 has the gate electrode coupled to the source of positive voltage level Vcc for serving as a resistor. When a defective memory cell is detected during a diagnostic operation, the fuse element 21 is destroyed with a laser beam.
The series combination has an output node 26 between the field effect transistors 22 and 23, and the output node 26 is connected to the input node of a CMOS inverter circuit 27 coupled between the source of positive voltage Vcc and the ground terminal. Between the output node 26 and the ground terminal is coupled an n-channel type field effect transistor 28 the gate electrode of which is coupled to the output node of the CMOS inverter circuit 27. The flip-flop circuit 24 thus arranged produces a replacing signal of the high voltage level at all times in the presence of the low voltage level at the output node 26 when the fuse element is destroyed. The replacing signal is fixed to the low voltage level, because the field effect transistor 28 turns on with the replacing signal of the high voltage level. However, if no destruction takes place in the fuse element 21, the p-channel type field effect transistor 22 is shifted between the high voltage level and the low voltage level depending upon the delayed chip select signal S1'. Namely, while the delayed chip select signal remains in the inactive high voltage level, the p-channel type field effect transistor 22 turns off to block a conduction path between the fuse element 21 and the output node 26, then the output node 26 remains in the low voltage level which in turn causes the CMOS inverter circuit 27 to shift the replacing signal to the high voltage level. On the other hand, if the delayed chip select signal S1' is shifted to the active low voltage level, the p-channel type field effect transistor 22 turns on to provide the conduction path between the fuse element 21 and the output node 26, then the output node 26 goes up to the high voltage level which allows the CMOS inverter circuit to shift the selection signal to the low voltage level.
The activation circuit 25 comprises an inverter circuit 29 and a series combination of transfer gates 30 and 31 coupled between two nodes to which the bit of the address signal ax.sub.i and the inverse thereof are respectively supplied. Since the replacing signal is supplied to the inverter circuit 29, the inverse of the replacing signal is produced by the inverter circuit 29. The replacing signal and the inverse thereof are supplied in parallel to the transfer gates 30 and 31. Then, the activation circuit 25 is responsive to the replacing signal and produces a selection signal identical in level with the bit ax.sub.i of the address signal of the active high voltage level in the presence of the replacing signal of the high voltage level. However, the inverse of the address bit ax.sub.i is transferred to the AND gate 12 if the replacing signal remains in the low voltage level.
The redundant memory activation circuit 9 is provided with a series combination of a fuse element 32, a p-channel type field effect transistor 33 and an n-channel type field effect transistor 34 coupled between the source of positive voltage level Vcc and the ground terminal as shown in FIG. 3, and a flip-flop circuit 35, and the flip-flop circuit 35 has a CMOS inverter circuit 36 coupled between the source of positive voltage level Vcc and the ground terminal and an n-channel type field effect transistor 37 coupled between an output node 38 of the series combination and the ground terminal.
The fuse element 32 is destroyed with the laser beam upon detection of the defective memory cell, and, for this reason, the output node 38 is fixed to the low voltage level regardless of the delayed chip select signal S1'. If the output node 38 is fixed to the low voltage level, the flip-flop circuit 35 produces an enable signal of the high voltage level at all times. However, when the fuse element 32 provides a conduction path between the source of positive voltage level Vcc and the p-channel type field effect transistor 33, the production of the enable signal depends upon the delayed chip select signal. Namely, when the delayed chip select signal S1' remains in the inactive high voltage level, the output node 38 is in the low voltage level due to the p-channel type field effect transistor 72 in the off state, then the CMOS inverter circuit 36 produces the enable signal, however, no data bit is read out from the semiconductor memory device due to the inactivated state. On the other hand, when the delayed chip select signal S1' goes down to the active low voltage level, the out put node 38 goes up to the high voltage level, then no enable signal is produced by the flip-flop circuit 35.
Turning back to FIG. 1 of the drawings, description is made for the replacement of the defective memory cell row with the redundant memory cell row 4. As described above, when the defective memory cell is detected, the fuse elements 21 and 32 are destroyed for replacement of the defective memory cell with the redundant memory cell. Then, the redundant memory activation circuit 9 produces the enable signal which is supplied to the AND gate 12. In this situation, if the address signal AD specifies the defective memory cell, all of the programming circuits 10 to 11 produces the selection signals of the high voltage level, respectively, which in turn are supplied to the AND gate 12. Then, the AND gate 12 produces the activation signal of the active high voltage level for activation of the redundant memory cell row 4. The activation signal is also supplied to the row address decoder circuit 7 for restricting the activation of the memory cell row, and, for this reason, no data bit is read out from the defective memory cell. However, the address signal AD does not specify the defective memory cell, at least one of the selection signals remains in the inactive low voltage level, then no activation signal is produced by the AND gate 12.
A problem is encountered in the prior-art semiconductor memory device in a large amount of current consumed therein. This is because of the fact that a conduction path is established in each series combination of the fuse element 21 or 32, the p-channel type field effect transistor 22 or 33 and the n-channel type field effect transistor 23 or 34 of the semiconductor memory device without any defective memory cell in the presence of the delayed chip select signal S1' of the active low voltage level. If a large number of the programming circuits are provided to cope with a high integration density which is one of the current tendencies in the semiconductor manufacturers, the problem becomes more serious.
Another semiconductor memory device is disclosed in U.S. Pat. No. 4,639,895, and a redundancy technique is employed in this semiconductor memory device.